FIGS. 35A, B and C show a conventional trench gate type IGBT and two types of diode structures, respectively. An n-buffer layer 15 in FIG. 35 has an impurity profile of ref. in FIG. 6A. Furthermore, FIGS. 35A, B and C are cross-sectional structure diagrams of an A″-A′″ line of a plan view of a power semiconductor chip shown in FIG. 1. As shown in FIGS. 1 and 35, the power semiconductor has the following four configurations.                Active cell region 1: a region for guaranteeing the basic performance of the power semiconductor chip.        Intermediate region 2: a region in which the active cell region 1 and an edge termination region 5 are joined to each other, and which is a region for guaranteeing breakdown resistance under dynamic operation of the power semiconductor and supporting the original performance of the active cell region 1.        Edge termination region 5: a region for retaining a withstand voltage under static state, guaranteeing the aspect of stability/reliability of a withstand voltage characteristic and suppressing breakdown resistance defective under dynamic operation to support the original performance of the active cell region.        Vertical Structure 35: a structure in which in addition to an n-drift layer 14, an n-buffer layer 15 and a p-collector layer 16 are contained in the IGBT of FIG. 35A, an n-buffer layer 15 and an n+-cathode layer 17 are contained in a diode of FIG. 35B, and an n-buffer layer 15, an n+-cathode layer 17 and a p-cathode layer 18 are contained in a diode of FIG. 35C. The n-drift layer is an n−-layer, but it is transcribed as “n-drift layer” for simplification. This structure is a region for guaranteeing the performance on a total loss which is a loss obtained by adding a loss under ON state, a loss under turn-on state and a loss under turn-off state, withstand voltage retention under static state, stability of a withstand voltage characteristic, an off-loss which is a leak characteristic at high temperature under withstand voltage retention, and guarantee of reliability aspect, and controllability and breakdown resistance under dynamic operation to support the basic performance of the power semiconductor.        
In the present IGBTs and diodes, Si wafers each of which is formed by an FZ (Floating Zone) method and typically has a concentration of an n-drift layer 14 required for each withstand voltage class of about 1.0×1012 to 1.0×1015 cm−3 is used as an Si wafer material, and the wafer process as shown in FIGS. 4 and 5 is executed. In the used wafer process, the thickness of a device (tdevice in FIG. 2: 40 to 700 μm in FIG. 2) required to retain a voltage required for a withstand voltage class during this wafer process is formed with high accuracy as shown in FIG. 4L or FIG. 5H, and a vertical structure 35 is configured during a wafer process shown in FIG. 4M or FIG. 5I.
The following two points may be considered as a background under which the wafer process of configuring the vertical structure during the wafer process by using the FZ wafer as described above is becoming a mainstream.                A wafer in which an n-drift layer 14 is manufactured by an epitaxial method has a demerit that the Si wafer cost remarkably increases depending on an Si thickness formed by the epitaxial method. Only the concentration of the n-drift layer 14 is set to a proper value for each withstand voltage class by the FZ method, and Si wafers including n-drift layers 14 having the same thickness irrespective of the withstand voltage class are used at the start time of the wafer process so that the Si wafer cost does not change. Therefore, it is necessary to adopt wafers low in unit cost.        For the purpose of actively using wafers to be manufactured by the FZ method, the thickness is controlled to a thickness required for a withstand voltage class in the wafer process to configure a vertical structure, thereby minimizing, to the utmost, wafer process steps corresponding to various wafer thicknesses which cause problems as a wafer process using large-diameter wafers of 8 to 12 inches, and realizing the manufacturing of power semiconductors such as IGBTs, diodes, etc. at large diameters.        
The impurity concentration of the n-drift layer 14 and the value of tdevice in FIG. 2 are device parameters which affect not only the withstand voltage characteristic of IGBTs or diodes, but also the total loss, and controllability and breakdown resistance under dynamic operation, and for which accuracy is required.
The details of the wafer process shown in FIGS. 4 and 5 have the same contents as described in PTLs 1 to 3. With respect to the vertical structure 35 configured in the wafer process as described above, the vertical structure 35 is formed in a step of FIG. 4L and a step of FIG. 5H and subsequently to an aluminum wiring step and a passivation film forming step. Therefore, for example in the case of IGBT, an MOS tr. structure is formed on a surface on which no vertical structure is formed, so that an aluminum wiring and a passivation film exist.
As a result, since an aluminum wiring exists on a surface on which no vertical structure is formed when diffusion layers 15 to 18 constituting a vertical structure are formed, the temperature is required to be set to a lower temperature than the melting point of metal. For example, the melting point of aluminum is equal to 660° C. There is used an annealing method for forming a temperature gradient in a device depth direction by using a laser having a wavelength at which no heat is transferred to a surface having no vertical structure thereon so that the temperature of the surface having no vertical structure thereon is set to a lower temperature than the melting point of metal. This annealing technique is a method called as laser anneal.
As a result, the impurity profile of the n-buffer layer 15 in an IGBT and a diode manufactured by the above-mentioned wafer process becomes a conspicuous impurity profile that has a shallow junction depth represented by Xj, nb1 which is equal to about 2.0 μm, and has a sharp impurity concentration gradient over the junction portion between the n-drift layer 14 and the n-buffer layer 15 like an impurity profile represented by ref. in FIGS. 6A and 6B. The impurity concentration gradient δnb1 as described above is equal to 4.52 decade cm−3/μm, for example.
In addition, the n-buffer layer 15 has such a feature on an n-layer forming process that an n-layer profile reproduces a profile in the depth direction in an ion implantation step of introducing impurities and diffusion in the depth direction and the lateral direction hardly occurs because the above-mentioned laser annealing technique is used.